TWI/TWI.h

#ifndef __TWI_H__
#define __TWI_H__


#if defined(ARDUINO) && (ARDUINO >= 100)
#else
#include <inttypes.h>
#endif

#define TWI_BUFFER_SIZE    20   



#define TWI_TWPS           0x00 ///< Prescaler = 0
#define TWI_TWBR           0x34 ///< TWI Bit rate Register setting.


union twi_status_reg 
{
  unsigned char all; 
  struct
  {
    unsigned char last_trans_ok:1; 
    unsigned char unused_bits:7;   
  };
};

extern union twi_status_reg twi_status_reg;

void twi_master_init( void );
unsigned char twi_busy_p( void );
unsigned char twi_get_state( void );
void twi_transmit( unsigned char * , unsigned char );
void twi_resend( void );
unsigned char twi_get_data( unsigned char *, unsigned char );


#define TWI_READ_BIT  0       ///< Bit position for R/W bit in "address byte".
#define TWI_ADR_BITS  1       ///< Bit position for LSB of the slave address 

#define TRUE          1
#define FALSE         0



#define TWI_START                  0x08  ///< START has been transmitted  
#define TWI_REP_START              0x10  ///< Repeated START has been transmitted
#define TWI_ARB_LOST               0x38  ///< Arbitration lost


#define TWI_MTX_ADR_ACK            0x18  ///< SLA+W has been transmitted and ACK received
#define TWI_MTX_ADR_NACK           0x20  ///< SLA+W has been transmitted and NACK received 
#define TWI_MTX_DATA_ACK           0x28  ///< Data byte has been transmitted and ACK received
#define TWI_MTX_DATA_NACK          0x30  ///< Data byte has been transmitted and NACK received 


#define TWI_MRX_ADR_ACK            0x40  ///< SLA+R has been transmitted and ACK received
#define TWI_MRX_ADR_NACK           0x48  ///< SLA+R has been transmitted and NACK received
#define TWI_MRX_DATA_ACK           0x50  ///< Data byte has been received and ACK transmitted
#define TWI_MRX_DATA_NACK          0x58  ///< Data byte has been received and NACK transmitted


#define TWI_STX_ADR_ACK            0xA8  ///< Own SLA+R has been received; ACK has been returned
#define TWI_STX_ADR_ACK_M_ARB_LOST 0xB0  ///< Arbitration lost in SLA+R/W as Master; 

#define TWI_STX_DATA_ACK           0xB8  ///< Data byte in TWDR has been transmitted; ACK has been received
#define TWI_STX_DATA_NACK          0xC0  ///< Data byte in TWDR has been transmitted; NOT ACK has been received
#define TWI_STX_DATA_ACK_LAST_BYTE 0xC8  ///< Last data byte in TWDR has been transmitted (TWEA = “0”); 





#define TWI_SRX_ADR_ACK            0x60  ///< Own SLA+W has been received ACK has been returned
#define TWI_SRX_ADR_ACK_M_ARB_LOST 0x68  ///< Arbitration lost in SLA+R/W as Master; own SLA+W has been received;

#define TWI_SRX_GEN_ACK            0x70  ///< General call address has been received; ACK has been returned
#define TWI_SRX_GEN_ACK_M_ARB_LOST 0x78  ///< Arbitration lost in SLA+R/W as Master; 


#define TWI_SRX_ADR_DATA_ACK       0x80  ///< Previously addressed with own SLA+W; data has been received; 

#define TWI_SRX_ADR_DATA_NACK      0x88  ///< Previously addressed with own SLA+W; data has been received; 

#define TWI_SRX_GEN_DATA_ACK       0x90  ///< Previously addressed with general call; data has been received; 

#define TWI_SRX_GEN_DATA_NACK      0x98  ///< Previously addressed with general call; data has been received; 

#define TWI_SRX_STOP_RESTART       0xA0  ///< A STOP condition or repeated START condition has been received 





#define TWI_NO_STATE               0xF8  ///< No relevant state information available; TWINT = “0”
#define TWI_BUS_ERROR              0x00  ///< Bus error due to an illegal START or STOP condition

#endif