Wiblocks --- TWI

TWI/TWI.h

00001 
00002 
00003 
00004 
00005 #ifndef __TWI_H__
00006 #define __TWI_H__
00007 
00008 
00009 #if defined(ARDUINO) && (ARDUINO >= 100)
00010 #else
00011 #include <inttypes.h>
00012 #endif
00013 
00018 #define TWI_BUFFER_SIZE    20   
00019 
00021 
00025 
00026 #define TWI_TWPS           0x00 ///< Prescaler = 0
00027 #define TWI_TWBR           0x34 ///< TWI Bit rate Register setting.
00028 
00029 
00033 union twi_status_reg 
00034 {
00035   unsigned char all; 
00036   struct
00037   {
00038     unsigned char last_trans_ok:1; 
00039     unsigned char unused_bits:7;   
00040   };
00041 };
00042 
00043 extern union twi_status_reg twi_status_reg;
00044 
00048 void twi_master_init( void );
00049 unsigned char twi_busy_p( void );
00050 unsigned char twi_get_state( void );
00051 void twi_transmit( unsigned char * , unsigned char );
00052 void twi_resend( void );
00053 unsigned char twi_get_data( unsigned char *, unsigned char );
00054 
00058 
00059 #define TWI_READ_BIT  0       ///< Bit position for R/W bit in "address byte".
00060 #define TWI_ADR_BITS  1       ///< Bit position for LSB of the slave address 
00061 
00062 #define TRUE          1
00063 #define FALSE         0
00064 
00068 
00072 
00073 #define TWI_START                  0x08  ///< START has been transmitted  
00074 #define TWI_REP_START              0x10  ///< Repeated START has been transmitted
00075 #define TWI_ARB_LOST               0x38  ///< Arbitration lost
00076 
00080 
00081 #define TWI_MTX_ADR_ACK            0x18  ///< SLA+W has been transmitted and ACK received
00082 #define TWI_MTX_ADR_NACK           0x20  ///< SLA+W has been transmitted and NACK received 
00083 #define TWI_MTX_DATA_ACK           0x28  ///< Data byte has been transmitted and ACK received
00084 #define TWI_MTX_DATA_NACK          0x30  ///< Data byte has been transmitted and NACK received 
00085 
00089 
00090 #define TWI_MRX_ADR_ACK            0x40  ///< SLA+R has been transmitted and ACK received
00091 #define TWI_MRX_ADR_NACK           0x48  ///< SLA+R has been transmitted and NACK received
00092 #define TWI_MRX_DATA_ACK           0x50  ///< Data byte has been received and ACK transmitted
00093 #define TWI_MRX_DATA_NACK          0x58  ///< Data byte has been received and NACK transmitted
00094 
00098 
00099 #define TWI_STX_ADR_ACK            0xA8  ///< Own SLA+R has been received; ACK has been returned
00100 #define TWI_STX_ADR_ACK_M_ARB_LOST 0xB0  ///< Arbitration lost in SLA+R/W as Master; 
00101 
00102 #define TWI_STX_DATA_ACK           0xB8  ///< Data byte in TWDR has been transmitted; ACK has been received
00103 #define TWI_STX_DATA_NACK          0xC0  ///< Data byte in TWDR has been transmitted; NOT ACK has been received
00104 #define TWI_STX_DATA_ACK_LAST_BYTE 0xC8  ///< Last data byte in TWDR has been transmitted (TWEA = “0”); 
00105 
00106 
00107 
00108 
00109 
00110 #define TWI_SRX_ADR_ACK            0x60  ///< Own SLA+W has been received ACK has been returned
00111 #define TWI_SRX_ADR_ACK_M_ARB_LOST 0x68  ///< Arbitration lost in SLA+R/W as Master; own SLA+W has been received;
00112 
00113 #define TWI_SRX_GEN_ACK            0x70  ///< General call address has been received; ACK has been returned
00114 #define TWI_SRX_GEN_ACK_M_ARB_LOST 0x78  ///< Arbitration lost in SLA+R/W as Master; 
00115 
00116 
00117 #define TWI_SRX_ADR_DATA_ACK       0x80  ///< Previously addressed with own SLA+W; data has been received; 
00118 
00119 #define TWI_SRX_ADR_DATA_NACK      0x88  ///< Previously addressed with own SLA+W; data has been received; 
00120 
00121 #define TWI_SRX_GEN_DATA_ACK       0x90  ///< Previously addressed with general call; data has been received; 
00122 
00123 #define TWI_SRX_GEN_DATA_NACK      0x98  ///< Previously addressed with general call; data has been received; 
00124 
00125 #define TWI_SRX_STOP_RESTART       0xA0  ///< A STOP condition or repeated START condition has been received 
00126 
00127 
00128 
00129 
00130 
00131 #define TWI_NO_STATE               0xF8  ///< No relevant state information available; TWINT = “0”
00132 #define TWI_BUS_ERROR              0x00  ///< Bus error due to an illegal START or STOP condition
00133 
00134 #endif